soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的，含蓄的

牛津词典

adj.

• 软性色情的；（性描写等）隐晦的，含蓄的
  showing or describing sexual activity without being too detailed or shocking

柯林斯词典

• (性描写)非赤裸裸的，较隐晦的
  Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

双语例句

• In practice, the designer can use this soft-core as a communication module through the FPGA implementation or to quickly build a Field Bus communication system to realize flexible CAN bus interface solutions.
  在实际应用中设计者可以将此软核作为通讯模块通过FPGA实现，或者快速搭建现场总线通信系统，实现灵活的CAN总线接口方案。
• SOPC includes soft-core or hard-core CPU 、 memory 、 I/ O and programmable logic resource, which has all the advantage of SOC 、 PLD and FPGA.
  SOPC综合了SOC、PLD和FPGA的优点，集成了硬核或软核CPU、存储器、I/O以及可编程逻辑。
• First, use of the system functions on a single chip design ideas, using a high-performance soft-core processor ( Nios II CPU) and IP multiplexing and improve the whole system to further improve the speed and flexibility.
  第一，运用了在单芯片上实现系统功能的设计思想，采用了高性能的软核处理器（NiosIICPU）和IP复用技术，提高了整个系统的运行速度和进一步改进的灵活性。
• Design and Implementation of Multi-channel Phone-billing-system Based upon NIOS Soft-core CPU
  基于NIOS软核CPU技术的多路电话计费系统的设计与实现
• Implementation of Soft-Core Processor and DDFS Based on FPGA
  基于FPGA的软核处理器及DDFS实现
• First some algorithms of gray-scale quantifying are analysised and simulated, and then the detailed designs of complex mold sub-module, quantifying sub-module and SDRAM soft-core controller is presented. 4.
  先对灰度量化算法进行了分析和仿真比较，然后详细介绍了复数求模子模块、量化子模块、SDRAM控制器的设计。
• The paper built a soft core processor which named NIOS II in the FPGA by using SOPC technology, and running μ C/ OS-ⅱ operating system on the NIOS II soft-core in order to achieve the scheduling of the system task.
  通过使用SOPC技术，在FPGA内部构建了NIOSⅡ软核处理器，并在NIOSⅡ软核上运行μC/OS-Ⅱ操作系统，从而实现了对系统任务的调度。
• This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU.
  提出了一种基于FPGA（现场可编程门阵列）和软核CPU的嵌入式系统设计的新方法。
• It inherits the hardcore, soft-core, DSP, memory, peripheral I/ O and programmable logic.
  它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。
• Research and Design of Soft-core IP for AVS Inter Decoder
  AVS帧间解码IP软核的研究与设计